// Protocol training
Every protocol on modern silicon.
From AMBA on-chip fabric to high-speed serial links – we cover the protocols semiconductor companies actually hire for.
// AMBA
3 protocolsAMBA on-chip buses
- APB
Low-power peripheral bus.
Read/write handshake · Non-pipelined transfers · Simple state machine
- AHB
High-performance system bus.
Pipelined burst transfers · Multi-master arbitration · Split & retry responses
- AXI
5-channel high-throughput bus.
Independent read/write channels · Out-of-order completion · QoS + region signalling
// Low-Speed
5 protocolsLow-speed peripherals
- UART
Async serial link.
Baud-rate generation · Framing, parity, stop bits · FIFOs + interrupts
- SPI
Full-duplex 4-wire link.
CPOL / CPHA modes · Master-slave chip selects · High-throughput short bursts
- I²C
2-wire multi-drop bus.
7/10-bit addressing · Clock stretching · Multi-master arbitration
- GPIO
General-purpose I/O.
Direction control · Edge/level interrupts · Alt-function muxing
- JTAG
Test access & debug.
TAP controller FSM · Boundary scan · Debug port for CPUs
// High-Speed
6 protocolsHigh-speed serial links
- PCIe
Serial expansion bus (Gen1–Gen7).
TLP / DLLP layers · LTSSM state machine · Virtual channels & QoS
- DDR
DDR3 / DDR4 / DDR5 memory.
Bank / row / column commands · Training + calibration · ECC & refresh
- USB
USB 2.0 / 3.x / 4.
Enumeration & descriptors · Device classes · Transaction types
- CXL
Cache-coherent accelerator link.
CXL.io / .cache / .mem · Coherency semantics · Host-device flows
- CHI
ARM coherent hub interface.
Snoop channels · MOESI-style coherency · Data-less transactions
- Ethernet
1G / 10G / 100G MAC + PHY.
MAC framing · PCS / PMA layers · PTP / TSN extensions
Learn any protocol in depth.
Protocol modules are bundled into the Design & Verification track and available as advance electives.