// 4 tracks · 15 modules · 14 protocols
Your silicon syllabus.
Four headline tracks — Physical Design, RTL Design, Design & Verification, Analog Design — each with basic, advance, and internship formats.
// Headline tracks
Pick your track.
// 14 protocols
Every protocol on modern silicon.
// AMBA
3 protocolsAMBA on-chip buses
- APB
Low-power peripheral bus.
Read/write handshake · Non-pipelined transfers · Simple state machine
- AHB
High-performance system bus.
Pipelined burst transfers · Multi-master arbitration · Split & retry responses
- AXI
5-channel high-throughput bus.
Independent read/write channels · Out-of-order completion · QoS + region signalling
// Low-Speed
5 protocolsLow-speed peripherals
- UART
Async serial link.
Baud-rate generation · Framing, parity, stop bits · FIFOs + interrupts
- SPI
Full-duplex 4-wire link.
CPOL / CPHA modes · Master-slave chip selects · High-throughput short bursts
- I²C
2-wire multi-drop bus.
7/10-bit addressing · Clock stretching · Multi-master arbitration
- GPIO
General-purpose I/O.
Direction control · Edge/level interrupts · Alt-function muxing
- JTAG
Test access & debug.
TAP controller FSM · Boundary scan · Debug port for CPUs
// High-Speed
6 protocolsHigh-speed serial links
- PCIe
Serial expansion bus (Gen1–Gen7).
TLP / DLLP layers · LTSSM state machine · Virtual channels & QoS
- DDR
DDR3 / DDR4 / DDR5 memory.
Bank / row / column commands · Training + calibration · ECC & refresh
- USB
USB 2.0 / 3.x / 4.
Enumeration & descriptors · Device classes · Transaction types
- CXL
Cache-coherent accelerator link.
CXL.io / .cache / .mem · Coherency semantics · Host-device flows
- CHI
ARM coherent hub interface.
Snoop channels · MOESI-style coherency · Data-less transactions
- Ethernet
1G / 10G / 100G MAC + PHY.
MAC framing · PCS / PMA layers · PTP / TSN extensions
// 15 modules
All course modules.
Digital Design Fundamentals
Number systems, Boolean algebra, logic gates, K-map, combinational & sequential circuits, FSMs, counters, shift registers.
Verilog HDL
Verilog syntax, modules, ports, RTL coding style, simulation & debug.
SystemVerilog
SystemVerilog OOP, interfaces, mailboxes, IPC, SVA assertions.
Randomization, Coverage & Assertions
Constraint randomization, functional/code coverage, SVA properties.
UVM Methodology
UVM components, phases, factory, TLM, sequences, RAL, virtual sequencer.
Physical Design (RTL → GDSII)
Complete PD flow on industry blocks: floorplan, placement, CTS, routing, signoff timing/DRC/LVS.
Analog Design
Analog transistor-level design & layout in Cadence Virtuoso.
AMBA Protocols
AMBA protocol family: APB, AHB, AXI — design & verification.
High-Speed Protocols
PCIe (Gen1-Gen7), USB, DDR, CXL, CHI, Ethernet architecture & verification.
Low-Speed Protocols
Bring-up, debug and verification of common low-speed peripherals.
Gate-Level Simulation (GLS)
Gate-level simulation methodology with SDF back-annotation.
IP Verification Flow
Test planning, environment, regression, coverage closure.
SoC Verification Flow
Full SoC verification: register verification, integration, connectivity.
Scripting & Automation
Perl, Python, Shell for DV automation & flow scripts.
Industry Projects
Hands-on APB & AXI SV/UVM verification projects.
// Track quiz
Q 1 / 5
Do you enjoy writing code more than running simulations?
// Live
Cost & EMI calculator
Total
₹94,400
includes 18% GST
EMI from
₹15,734 /mo
0% interest · partner NBFC