PR
Priya Raghavan
NVIDIA
DV Engineer
22 LPA
// Alumni Wall
5000+ engineers shipping silicon.
These are real MasterVLSI graduates — names, roles, packages, companies. Filter by the track they took to see who's landed where.
AM
Arjun Menon
AMD
Physical Design Engineer
21 LPA
SK
Sneha Kulkarni
Qualcomm
RTL Designer
19 LPA
VI
Vikram Iyer
Intel
DV Engineer
24 LPA
AS
Ananya Shah
Synopsys
STA Engineer
18 LPA
RB
Rohit Bansal
Samsung
SoC Verification Lead
28 LPA
KS
Karthik Subramaniam
Marvell
ASIC Engineer
24 LPA
MJ
Meera Joshi
Texas Instruments
UVM Engineer
19 LPA
AK
Adithya Krishnan
MediaTek
RTL Lead
28 LPA
PR
Pooja Reddy
Renesas
Analog Designer
17 LPA
SM
Saurabh Mehta
Cadence
Physical Design Engineer
22 LPA
NS
Neha Sharma
Broadcom
DV Engineer
20 LPA
RV
Rahul Verma
Micron
DDR Verification
23 LPA
DN
Divya Nair
Analog Devices
Analog Designer
19 LPA
VP
Vishnu Prasad
STMicroelectronics
RTL Designer
18 LPA
SG
Shreya Gupta
Xilinx / AMD
FPGA / DV
20 LPA
AR
Aditya Rao
NXP Semiconductors
SoC Integration
21 LPA
KM
Kavya Menon
Bosch
DV Engineer
17 LPA
MA
Manish Agarwal
Intel
Physical Design
23 LPA
SR
Sanjana Rao
NVIDIA
GLS Verification
21 LPA
RK
Ravi Kumar
Qualcomm
Physical Design
20 LPA
DS
Deepa Suresh
Wipro Semiconductor
RTL Verification
16 LPA
NR
Naveen Reddy
Tessolve
IP Verification
15 LPA
AK
Anjali Kapoor
Cadence
Analog Layout
18 LPA
Showing 24 of 5000+ placements. Real photos rolling out as we digitise the archive.
You could be next on this wall.
Join the next cohort. Placement starts within 30–45 days of the core modules.