MasterVLSI

// Free learning

VLSI on YouTube.

200+ videos, organised by topic. Verilog basics through to UVM, PD, STA, DFT and full interview prep — all from working industry mentors. Start anywhere, work at your own pace.

playlists
cheatsheet

// Cheatsheet

VLSI Glossary

  • RTLRegister Transfer LevelDesign

    Abstraction describing the flow of data between registers and the logic between them.

  • UVMUniversal Verification MethodologyDV

    SystemVerilog class library standardising reusable testbench architecture.

  • STAStatic Timing AnalysisTiming

    Vector-less analysis of timing paths across PVT corners.

  • DFTDesign for TestTest

    Adding scan, BIST and ATPG hooks so silicon can be tested post-fab.

  • CTSClock Tree SynthesisPD

    Buffering and balancing clock distribution to minimise skew.

  • OCVOn-Chip VariationTiming

    Modeling derates that account for systematic/random process variation.

  • UPFUnified Power FormatLow Power

    Side-file describing power intent — domains, isolation, retention.

  • AMBAARM AMBABus

    Standard on-chip bus family — AHB, APB, AXI.

  • GDSIIFab

    Binary stream format for chip layout — the file that goes to the foundry.

  • ECOEngineering Change OrderPD

    Post-route incremental fixes — metal or full ECO.

  • MBISTMemory BISTTest

    Built-in self-test logic that exercises on-chip memories.

  • PSSPortable Stimulus StandardDV

    Accellera spec for portable, intent-level test scenarios.

200+ free videos. Zero excuses.

Subscribe and ring the bell — new mentor-led tutorials drop every week.