Low Power Design: UPF, Clock Gating & Beyond

The big three

• Clock gating – kill the clock to idle flops. Free 20% dynamic power.
• Power gating – shut off whole blocks via header/footer cells.
• Multi-V_DD – run slow blocks at low voltage, fast blocks at high.

UPF in 30 seconds

A separate file describes power intent (domains, supplies, level shifters, isolation). Tools then enforce it through synthesis, PD, and verification. Never hand-instantiate isolation cells – let UPF do it.