DFT 101: Scan Chains, BIST, and ATPG

Scan chains

Replace every flop with a scan flop. Stitch them into long shift registers. Now you can shift in any state, run a capture cycle, and shift it out.

BIST / MBIST

The chip tests itself at speed. Critical for memories – you cannot externally test a 100 GB/s SRAM.

ATPG coverage

Modern designs target >99% stuck-at + >95% transition coverage. Anything less and your yield curve looks ugly.