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Blocking vs Non-Blocking Assignments: The #1 Interview Trap

One mixing rule separates RTL engineers from sim-only coders. Three code examples that fail, and the rule that fixes them all.

MasterVLSI Team·June 16, 2026· 6 min
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// RTL6 min

Blocking vs Non-Blocking Assignments: The #1 Interview Trap

Jun 16, 2026 · MasterVLSI Team

The one rule

Blocking (=) in combinational blocks. Non-blocking (`<=)) in sequential blocks. Never in the same block.

Every race condition, every 'works in sim, dies in silicon' mystery, and most x-propagation bugs trace back to a violation of this single line.

Trap 1: the same-signal swap

always_ff @(posedge clk) begin
  a = b;
  b = a;   // if a and b are driven here, you just made a copy, not a swap
end

Blocking executes in order: the second statement sees the first's result. Non-blocking defers all updates to the end of the time step, so both flops sample the old values – the behavior you actually want from a flip-flop.

Trap 2: the self-checking counter

always_ff @(posedge clk)
  if (en) count = count + 1;

In simulation this appears to work – until two different signals assign count in the same step and the last-writer wins based on file order, not hardware order. Two drivers on one net is a hardware contradiction the simulator happily executes.

Trap 3: mixed block, silent mismatch

always_ff @(posedge clk) begin
  q <= d;
  tmp = q;   // sampling q AFTER the <= scheduling? order games begin
end

Mix the styles and the tool's interpretation of tmp depends on where the simulator schedules the NBA – identical RTL can simulate differently across tools. Synthesis often saves you; timing closes wrong.

Why the simulator behaves that way

Verilog simulation runs in three steps: active (blocking, LHS updated immediately), NBA (non-blocking LHS updates, deferred), then reactive. A flop's output must not change until all inputs for the edge have been evaluated – that's the NBA. Blocking in a sequential block breaks that contract, which is why the simulator produces order-dependent results and the synthesizer produces hardware that doesn't match.

The interview version

When asked, walk through: scheduling semantics → race example → synthesis reality → the rule. Interviewers who ask this question are not testing your memory of the rule – they are testing whether you can explain why in two minutes. If you mention the NBA queue by name, you pass.

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