Top 20 Verilog Interview Questions with Answers

The fundamentals

1. Blocking vs non-blocking – when and why? always_comb for blocking, always_ff for non-blocking. Non-blocking (<=) schedules the assignment for the end of the time step, so every flop samples the pre-edge value – no races. Blocking (=) evaluates inline and is only safe in combinational logic. Mixing them in one block creates simulation/synthesis mismatch.

2. What does synthesis infer from a signal you never assign? A latch. Every un-assigned path in a combinational block implies "hold the last value", and synthesis faithfully builds storage. That is why every case must be fully specified – default, else, or casez with a default.

3. Difference between case, casez and casex? casez treats ? as don't-care, casex treats x and z as don't-care. Synthesis can collapse parallel branches if you aren't careful – keep one priority-encoded branch per selector.

Design questions

4. What is a race condition in simulation? Two blocking assignments to the same variable in the same time step, order-dependent. The classic: a = b; b = a; – swap or no swap depends on statement order. Non-blocking assignments eliminate the ambiguity.

5. Explain how a synchronous FIFO works. Read and write pointers into dual-port RAM. full = (wptr == rptr) && write-request pending, empty = (wptr == rptr) with no pending read. The same pointer can mean full or empty – the condition you checked at the edge disambiguates.

6. How would you build a clock divider? A counter that toggles on a terminal count gives 50% duty only for even divides. For odd divides you need two counters (posedge and negedge) and an OR – or a small FSM.

7. What is metastability, and the standard cure? A flip-flop sampling a changing input inside its setup/hold window outputs an unknown state. Two cascaded flops (the synchronizer) allow a full clock period for the first flop to resolve before the logic sees the value. It never removes the risk – it makes the failure probability negligible.

8. Moore vs Mealy FSM? Moore: outputs depend only on state (safer, one more cycle latency). Mealy: outputs depend on state and inputs (faster response, glitch-prone). Interviews usually want the trade-off, not a definition.

9. When would you pipeline a combinational path? When the critical path exceeds the clock period. Splitting a 20-gate chain into two 10-gate stages doubles throughput at the cost of two-cycle latency. The follow-up is always: "where did the register move?" – always through the data path, never through the control.

Synthesis traps

10. Why does for loop in Verilog need a compile-time bound? Because it's an unrolling hint, not a runtime loop. The synthesizer replicates the body per iteration – a data-dependent bound would need runtime hardware of unknown size.

11. What happens if you leave an else off an if inside always_ff? Nothing – the flop already stores state, and the absence of else just means "keep". The latch trap only bites in combinational blocks.

12. wire vs reg – which survives synthesis? Neither. They are simulation-only declarations. Synthesis cares about what the logic is – storage or combinational – not the keyword.

The panel questions

13. What is $signed and when does it matter? Bit-width and sign extension. 8'shFF extended to 16 bits is 16'h00FF as unsigned but 16'hFFFF as signed. Arithmetic compare bugs come from forgetting to sign-consistently extend both operands.

14. Explain generate with a practical use. Conditional or loop elaboration at compile time – instantiate a FIFO bank of width depending on a parameter, or a daisy-chain of flops. It is textual replication with parameters, nothing more.

15. What is the difference between function and task? Functions return a value, execute in zero time, and may not use # delays. Tasks may return nothing, may consume time, and may not be called from within an expression.

16. How do you check for glitches on a clock? Glitch = multiple transitions within one clock period. Detection: monitor for more than one edge in a period, or use a fast reference clock to sample the suspect clock and flag any cycle with both edges.

17. What's the first thing you check when a design works in sim but fails on silicon? Clock. Then reset. Then CDC boundaries. In that order – all three are simulation-blind to real silicon behavior, and all three are cheap to verify with a focused bring-up script.

18. Reset strategy – async vs sync? Async reset is immediate and doesn't need a clean clock, but deassertion must be synchronized to avoid recovery/removal violations. Sync reset is simpler to analyze but needs a free-running clock. Modern designs: async assert, sync deassert.

19. What is initial used for in synthesizable code? Almost nothing. Some tools use it for FPGA RAM init or ROM contents. If you need reset values, make them explicit with the reset signal – initial values are a simulation convenience.

20. What question should you ask the interviewer? "Where is the critical path in the last chip you shipped, and how did you close it?" A real design team answers instantly – a proxy team goes quiet. This one question has saved more candidates than any coding trick.

The pattern interviewers look for: not memorised answers, but the why. Every answer above earns more credit if you follow it with one sentence of when-it-breaks.