Back to blog
Physical DesignBackend
Physical Design Flow: Floorplan to GDSII
The seven-step PD recipe – what each tool does, what can go wrong, and what to fix first.
MasterVLSI Team·November 18, 2025· 9 min
Share
// Physical Design9 min
Physical Design Flow: Floorplan to GDSII
Nov 18, 2025 · MasterVLSI Team
The PD recipe
- Floorplan – die size, macro placement, pin assignment
- Power planning – straps, rings, mesh
- Placement – standard cells with timing in mind
- CTS – clock tree synthesis, skew balancing
- Routing – global then detail, with DRC awareness
- Signoff STA – multi-corner, multi-mode
- Physical verification – DRC, LVS, antenna, ERC
The #1 floorplan mistake
Macro placement before understanding dataflow. Always sketch the connectivity graph first.
Got questions about this topic?
Ping us on WhatsApp – our mentors usually reply within the hour.
Chat with us